The formation of electrical contacts to electronic and memory devices is a considerable challenge as the integration density of these devices is increased as a consequence of technology scaling. For example, the projected contact pitch for the 32 nm, 22 nm, and 15 nm nodes are 130 nm, 100 nm, and 80 nm respectively. Alignment of the contact to the source, drain, and gate of the device is critical. In particular, misalignment of the source and drain contacts with respect to the gate can cause electrical shorts, rendering the device inoperable.
Therefore a need exists to overcome the problems with the prior art as discussed above.